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CY62148V MoBL
4M (512K x 8) Static RAM
Features
* * * * * * * Wide voltage range: 2.7V-3.6V Ultra low active power Low standby power TTL-compatible inputs and outputs Automatic power-down when deselected CMOS for optimum speed/power Package available in a 32 pin TSOPII and a 32-pin SOIC package also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can be put into standby mode when deselected (CE HIGH). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW).
Functional Description[1]
The CY62148V is a high-performance CMOS static RAM organized as 512K words by eight bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL) in portable applications such as cellular telephones. The device
Logic Block Diagram
Data in Drivers
I/O0 I/O1
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
ROW DECODER
SENSE AMPS
I/O2 I/O3 I/O4 I/O5
512K x 8 ARRAY
CE WE OE
COLUMN DECODER
POWER DOWN
I/O6 I/O7
Note: 1. For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05070 Rev. *A
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3901 North First Street
A10 A 11 A 12 A13 A14 A15 A16 A17 A18
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San Jose
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CA 95134 * 408-943-2600 Revised August 27, 2002
CY62148V MoBL
Pin Configurations
TSOPII/SOIC Top View A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O 5 I/O4 I/O3
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-65C to +150C Ambient Temperature with Power Applied............................................... 55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[2] ....................................-0.5V to VCC + 0.5V
DC Input Voltage[2] ................................ -0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Range Industrial Ambient Temperature -40C to +85C VCC 2.7V to 3.6V
Product Portfolio
Power Dissipation VCC Range (V) Product CY62148VLL Min. 2.7 Typ.[3] 3.0 Max. 3.6 Speed (ns) 70 Operating ICC, (mA) Typ.[3] 7 Maximum 15 2 Standby ISB2, (A) Typ.[3] Maximum 20
Electrical Characteristics Over the Operating Range
CY62148V-70 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current VCC Operating Supply Current Automatic CE Power-down Current-- CMOS Inputs Automatic CE Power-down Current-- CMOS Inputs GND < VI < VCC IOUT = 0 mA, f = fMAX = 1/tRC CMOS Levels VCC = 3.6V IOH = -1.0 mA IOL = 2.1 mA Test Conditions VCC = 2.7V VCC = 2.7V VCC = 3.6V VCC = 2.7V 2.2 -0.5 -1 -1 +1 +1 7 1 2 Min. 2.4 0.4 VCC + 0.5V 0.8 +1 +1 15 2 20 Typ.[3] Max. Unit V V V V A A mA mA A
Output Leakage Current GND < VO < VCC, Output Disabled
IOUT = 0 mA, f = 1 MHz CMOS Levels ISB1 CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V, f = fMAX CE > VCC - 0.3V VIN > VCC - 0.3V or VIN < 0.3V, f = 0 VCC = 3.6V
ISB2
Notes: 2. VIL(min.) = -2.0V for pulse durations less than 20 ns. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C.
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CY62148V MoBL
Capacitance[4]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.0V Max. 6 8 Unit pF pF
Thermal Resistance
Parameter JA JC Description Thermal Resistance[4] (Junction to Ambient) Thermal Resistance[4] (Junction to Case) Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board Others TBD TBD BGA TBD TBD Units C/W C/W
AC Test Loads and Waveforms
R1 VCC OUTPUT 50 pF INCLUDING JIG AND SCOPE R2 VCC TYP 10% GND Rise time: 1V/ns Equivalent to: THEVENIN EQUIVALENT Rth OUTPUT Vth ALL INPUT PULSES 90% 90% 10% Fall time: 1V/ns
Parameters R1 R2 RTH VTH
3.0V 1105 1550 645 1.75V
Unit Ohms Ohms Ohms Volts
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR tCDR[4] tR[5] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = 1.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V; No input may exceed VCC + 0.3V 0 tRC Conditions Min. 1.0 0.2 Typ.[3] Max. 3.6 5.5 Unit V A ns ns
Data Retention Waveform
DATA RETENTION MODE VCC 1.0V tCDR CE VDR > 1.0 V 1.0V tR
Notes: 4. Tested initially and after any design or process changes that may affect these parameters. 5. Full-device AC operation requires linear VCC ramp from VDR to VCC(min.) > 10 s or stable at VCC(min.) > 10 s.
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CY62148V MoBL
Switching Characteristics Over the Operating Range
Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle[9, 10] tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High-Z
[7, 8] [6]
CY62148V-70 Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z[7] OE HIGH to High-Z[8] 10 25 0 70 70 60 60 0 0 50 30 0 25 10
[7, 8]
Min. 70
Max.
Unit ns
70 10 70 35 5 25
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CE LOW to Low-Z[7] CE HIGH to High-Z CE LOW to Power-up CE HIGH to Power-down
WE HIGH to Low-Z[7]
Switching Waveforms
Read Cycle No. 1 [11, 12]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Notes: 6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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CY62148V MoBL
Switching Waveforms (continued)
Read Cycle No. 2 [12, 13]
CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50%
[9, 14, 15]
tRC
tHZOE tHZCE DATA VALID tPD
HIGH IMPEDANCE
DATA OUT
ICC 50% ISB
Write Cycle No. 1 (WE Controlled)
tWC ADDRESS
CE tAW WE tSA tPWE tHA
OE tSD DATA I/O NOTE 16 tHZOE DATAIN VALID tHD
Write Cycle No. 2 (CE Controlled)
[9, 14, 15]
tWC ADDRESS CE tSA tAW WE tSD DATA I/O DATAIN VALID tHD tHA tSCE
Notes: 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 16. During this period, the I/Os are in output state and input signals should not be applied.
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CY62148V MoBL
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
[10, 15]
tWC ADDRESS
CE tAW WE tSA tHA
tSD DATA I/O NOTE 16 tHZWE DATAIN VALID
tHD
tLZWE
Typical DC and AC Characteristics
1.4 1.2 1.0 ISB (A) ICC 0.8 0.6 0.4 0.2 0.0 1.7 2.2 2.7 3.2 SUPPLY VOLTAGE (V) 3.7 Normalized Operating Current vs. Supply Voltage Standby Current vs. Supply Voltage 45 40 35 30 25 20 15 10 1.0 3.7 2.8 1.9 SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage 80 70 60 50 TAA (ns) 40 30 20 10 1.0 2.8 1.9 SUPPLY VOLTAGE (V) 3.7
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CY62148V MoBL
Truth Table
CE H L L L WE X H L H OE X L X H Inputs/Outputs High-Z Data Out Data In High-Z Read Write Output Disabled Mode Deselect/Power-down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 70 Ordering Code CY62148VLL-70ZI CY62148VLL-70SI Package Name ZS32 S34 32-lead TSOPII 32-lead 450-mil. molded SOIC Package Type Operating Range Industrial
Package Diagrams
32-Lead (450-mil) Molded SOIC S34
51-85081-A
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CY62148V MoBL
Package Diagrams (continued)
32-lead TSOP II ZS32
51-85095
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62148V MoBL
Document Title: CY62148V MoBL 4M (512K x 8) Static RAM Document Number: 38-05070 REV. ** *A ECN NO. Issue Date 107263 116515 09/15/01 09/04/02 Orig. of Change SZV GBI Description of Change Changed from Spec number: 38-00646 to 38-05070 Added footnote 1. Deleted fBGA package. Removed fBGA package (replacement fBGA package is available in CY62148CV30)
Document #: 38-05070 Rev. *A
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